<rss xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title>MIPS - 标签 - HAKULA†CHANNEL</title><link>https://old.hakula.xyz/tags/mips/</link><description>MIPS - 标签 - HAKULA†CHANNEL</description><generator>Hugo -- gohugo.io</generator><language>zh-CN</language><managingEditor>i@hakula.xyz (Hakula)</managingEditor><webMaster>i@hakula.xyz (Hakula)</webMaster><lastBuildDate>Mon, 08 Jun 2020 05:46:00 +0800</lastBuildDate><atom:link href="https://old.hakula.xyz/tags/mips/" rel="self" type="application/rss+xml"/><item><title>计组 - Lab 4: 分支预测</title><link>https://old.hakula.xyz/posts/note/comp-org/mips-branch-predictor/</link><pubDate>Mon, 08 Jun 2020 05:46:00 +0800</pubDate><author>Hakula</author><guid>https://old.hakula.xyz/posts/note/comp-org/mips-branch-predictor/</guid><description><![CDATA[<div class="featured-image">
                <img src="https://hakula-1257872502.file.myqcloud.com/images/3/article-covers/36cb9956-2a49-4784-a3a3-785afe0f5af1_78954079.webp" referrerpolicy="no-referrer">
            </div><p>动态分支预测器，实现了一个 2 位 Tournament Predictor，其中包含一个 Global Predictor、一个 Local Predictor 和一个 Static Predictor，使用 SystemVerilog 编写。</p>
<p>Introduction to Computer Systems II (H) @ Fudan University, spring 2020.</p>]]></description></item><item><title>计组 - Lab 3: Cache</title><link>https://old.hakula.xyz/posts/note/comp-org/mips-cache/</link><pubDate>Sun, 24 May 2020 16:36:00 +0800</pubDate><author>Hakula</author><guid>https://old.hakula.xyz/posts/note/comp-org/mips-cache/</guid><description><![CDATA[<div class="featured-image">
                <img src="https://hakula-1257872502.file.myqcloud.com/images/3/article-covers/46dfc5c0-b5e8-4228-bd48-5dfeed2c2a17_78302689.webp" referrerpolicy="no-referrer">
            </div><p>32 位 256 bytes 4 路组相联（参数可调节）高速缓存，使用 SystemVerilog 编写。</p>
<p>Introduction to Computer Systems II (H) @ Fudan University, spring 2020.</p>]]></description></item><item><title>计组 - Lab 2: 流水线 MIPS CPU</title><link>https://old.hakula.xyz/posts/note/comp-org/pipeline-mips-cpu/</link><pubDate>Sat, 25 Apr 2020 04:37:00 +0800</pubDate><author>Hakula</author><guid>https://old.hakula.xyz/posts/note/comp-org/pipeline-mips-cpu/</guid><description><![CDATA[<div class="featured-image">
                <img src="https://hakula-1257872502.file.myqcloud.com/images/3/article-covers/8743ce77-9e13-40f5-9040-dcfa901db1d9_75293213.webp" referrerpolicy="no-referrer">
            </div><p>32 位流水线 MIPS 指令集 CPU，使用 SystemVerilog 编写。</p>
<p>Introduction to Computer Systems II (H) @ Fudan University, spring 2020.</p>]]></description></item><item><title>计组 - Lab 1: 单周期 MIPS CPU</title><link>https://old.hakula.xyz/posts/note/comp-org/single-cycle-mips-cpu/</link><pubDate>Tue, 07 Apr 2020 23:14:00 +0800</pubDate><author>Hakula</author><guid>https://old.hakula.xyz/posts/note/comp-org/single-cycle-mips-cpu/</guid><description><![CDATA[<div class="featured-image">
                <img src="https://hakula-1257872502.file.myqcloud.com/images/3/article-covers/06449c5c-93cb-4fe9-b158-5ea714ce2fec_78398601.webp" referrerpolicy="no-referrer">
            </div><p>32 位单周期 MIPS 指令集 CPU，使用 SystemVerilog 编写。</p>
<p>Introduction to Computer Systems II (H) @ Fudan University, spring 2020.</p>]]></description></item></channel></rss>